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MIPI interface introduction, SONY FCB-EV9500M equipped with MIPI network control board features

The emergence of Mobile Industry Processor Interface (MIPI) aims to standardize the internal interfaces of mobile phones, such as camera, display interface, RF/baseband interface, etc., so as to reduce the complexity of mobile phone design and increase design flexibility. MIPI CSI is designed to provide a high-speed serial interface between HD cameras and application processors, such as the CSI protocol used between cameras and cpus in current smartphones. Currently, the second version, CSI-2, is widely used, and the latest version is CSI-3. MIPI is not a single interface or protocol, but a set of protocols and standards to meet the unique requirements of various subsystems (image subsystem [camera and display], storage subsystem, wireless subsystem, power management subsystem, low bandwidth subsystem). Unlike traditional interfaces, which are associated with multiple physical layers, MIPI interfaces only connect to D-PHY or M-PHY when needed.

MIPI interface introduction, SONY FCB-EV9500M equipped with MIPI network control board features - Sony Camera Information - 1

SONY FBB-EV9500M camera movement is MIPI interface, equipped with Xuanzhan technology independent research and development of MIPI network control board, not only a collection of MIPI interface speed, large amount of data transmission, low power consumption, strong anti-interference and other advantages, It also has the advantages of converting the video of the camera into video signal, directly controlling the camera through the Internet IE interface, supporting Bluetooth, WIFI, 4G function module expansion, greatly improving the ease of operation and convenience of FCB-EV9500M.

The MIPI CSI-2 protocol can use either D-PHY, which is consistent with DSI, or C-PHY as the physical layer protocol. CSI-3, on the other hand, can only use M-PHY as the physical layer protocol, which means that CSI-2 and CSI-3 are incompatible! DSI defines a high-speed serial interface between the processor and the display module. CSI defines a high-speed serial interface between the processor and the camera module. D-PHY: Provides the physical layer definition of DSI and CSI. Generally, both CSI-2 and DSI require a maximum of 6 signals. The number of signals depends on the number of lines used by the designer. In addition, CSI-2 and DSI share a common physical interface called D-PHY, which is designed to improve efficiency and reduce power consumption and EMI.

The Mipi CSI is mainly for cameras. In addition to the ground wire, MIPI CSI2 generally has one pair of I2C communication pins, one pair of MIPI differential clock pins and one to four pairs of MIPI differential data signal pins.

Layered Structure of MIPI CSI2 There are several layered methods of MIPI CSI2. According to the specification of MIPI Alliance, CSI2 can be divided into five layers, namely, application layer, packet/unpacket layer, Low Level Protocol layer, channel management layer and physical layer.

MIPI interface introduction, SONY FCB-EV9500M equipped with MIPI network control board features - Sony Camera Information - 2

Working mode of MIPI CSI2

D-PHY has two transmission modes:

(1) HS high-speed transmission mode, used for transmitting burst data, synchronous transmission, signal is differential signal, level range is 100mv-300mv, transmission speed range is 80-1000Mbps. In this mode of transmission, when the positive end of the difference line receives 1.2V signal and the negative end receives 0V signal, the receiver is recognized as 1. Otherwise, it is 0.

(2) LP low power mode, used for transmission control instructions, asynchronous transmission, the signal line is single-ended, the level range is 0-1.2v, no clock line, the clock is xOR through two data lines, the speed is only 10Mbps. When transmitting in this mode, the receiver is identified as 1 when the positive end receives 300m V and the negative end receives 100m V. Otherwise, it is identified as 0.

Packet Format of MIPI CSI2 MIPI CSI2 is a byte-oriented, packet-based protocol. It supports the transmission of data of any size through short packet and long packet formats. Each packet is separated by the EOT-LPS-SOT sequence.

There are two types of LLP packages: long and short. The transmission of each packet starts with SoT (start of transmission) and ends with EoT (end of transmission), with LPS (Low Power State) in between. Long packet Format of MIPI CSI2 Long packet of MIPI CSI2 mainly consists of three parts: packet header, data packet and packet tail. The packet header can be subdivided into data identifier, packet size word count and error check code (ECC).

The data identifier is 1 byte in size and contains the virtual data channel number [7:6] and data type [5:0]. The size of a data packet is 2 bytes, and its content is the length of the transmitted data in “words”. The error check code is 1 byte in size and is responsible for checking and correcting the transmission errors of data packets. The size of the data packet can be 0~65535 bytes. The packet tail size is 2 bytes and is the check sum of the data load. The short packet format of MIPI CSI2 is compared to the long packet, which has no data packet and no packet tail. The data type in the data id DI is between 0x00 and 0x0F. The WC field is the data field of the short packet, which can be defined by the user. ECC is a check code, which can correct 1bit errors and check 2bit errors.

 

 

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